As integrated circuits are produced with greater and greater levels of circuit density, efficient testing schemes that guarantee high fault coverage while minimizing test costs and chip area overhead have become essential. The number of transistors that can be placed on a chip has been doubling roughly every eighteen months, as predicted by Moore's law. The amount of data required to test such massively complex chips has been increasing even more rapidly. In practical terms, for very large integrated circuits, the test cost is approaching (and may even exceed) the design cost.
Many integrated circuits are tested using structured design-for-testability (DFT) techniques, which employ the general concept of making some or all state variables (e.g., memory elements, such as flip-flops and latches) directly controllable and observable. Preferably, a circuit is treated, as far as testing of combinational faults is concerned, as a combinational or a nearly combinational network. The most-often used DFT methodology assumes that during testing all (or almost all) memory elements are connected to form one or more shift registers termed “scan chains.”
A circuit that utilizes scan chains for testing typically has two basic modes of operation: a normal mode and a test (or scan) mode. In the normal mode, the memory elements perform their regular functions. In the scan mode, the memory elements become scan cells that are connected to form a number of scan chains. During a typical test cycle, the scan chains are first operated in the scan mode in order to shift a test pattern into the circuit. The circuit is then operated in normal mode for one or more clock cycles in order to capture the circuit's functional response to the test pattern. Finally, the scan chains are operated in the scan mode in order to shift out the circuit's response to the test patterns. The test response can then be compared to a fault-free response to determine if the circuit-under-test (CUT) works properly.
Scan design methodology has gained widespread adoption by virtue of its simple automatic test pattern generation (ATPG) and silicon debugging capabilities. Today, ATPG software tools are so efficient that it is possible to generate test sets (a collection of test patterns) that guarantee almost complete fault coverage for several types of faults, including stuck-at and transition faults. It is also possible to target other faults, such as path delay and bridging faults.
Typically, when a test pattern is generated by an ATPG tool, only a small number of scan cells (e.g., 2-5%) need to be specified in order to detect the targeted faults. The remaining scan cells in the scan chains can then be filled with random binary values. This results in a test pattern comprising a small portion of deterministically specified test values (also referred to as “deterministic test values”) and a large portion of randomly specified test values. Thus, although the test pattern is considered to be fully specified, only a small fraction of the pattern comprises test values used explicitly to test the targeted faults.
In general, an ATPG tool relies on effective fault models to produce test patterns that guarantee coverage of a targeted fault. A fault model typically comprises a logic-level abstraction of circuit behavior in the presence of a circuit fault, such as a physical defect. One of the most widely used fault models for generating test patterns is the single stuck-at-line (“SSL” or “stuck-at”) fault model. Although the SSL fault model has been used for many years with proven effectiveness and robustness, it is becoming less effective due to continuously shrinking feature sizes and more complex fabrication processes. Further, the smaller feature sizes and more complex processes create a greater potential for physical defects, such as bridging or bridging-type defects. Existing test patterns generated using the SSL fault model, however, do not adequately cover bridging or bridging-type defects. Such defects can comprise, for example, defects that result in bridges between signal nodes of the circuit (having either low or high resistivity) and physical or design defects that create cross-talk effects between signal nodes of the circuit. It has been shown, for example, that certain test sets having greater than 95% SSL fault coverage produce only 33% coverage of node-to-node bridging faults. Accordingly, there is a need for enhanced test-pattern-generation techniques.